A Fast Parallel Huffman Decoder for Fpga Implementation

The paper presents a novel algorithm and architecture for implementing a Huffman decoder. It starts with an overview of the basics, from the entropy coding and the way the Huffman coding is obtained, to the way a Huffman coder handles data and image components within the Jpeg standard. Then it briefly discusses the decoding procedures proposed by the ISO/IEC 109181(1993E) standard; due to their sequential nature, a decoder that simply implements these procedures requires several execution cycles to output one set of decoded data. A new decoding algorithm is then introduced, based on a parallel architecture that allows it to output a set of decoded data per each clock cycle. This approach was validated through actual implementation on an of-theshelf FPGA; this not only demonstrates the proposed algorithm and architecture but also proves that it can operate at very high frequencies, up to 100MHz. A limitation of this implementation is the relatively large amount of hardware resources it requires.